this is the code of my make file
obj-m +=hello-1.o all: <tab>make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules clean: <tab>make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
AND I HAVE FEW QUESTIONS
- we save C language file with extension *.c so for Makefile which extension should we use?
- When i throw command in terminal “make” it gives me error that make: Nothing to be done for `all’.
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Answer
Probably the file all
already exists. As it doesn’t depend on anything, and isn’t a dependency of .PHONY
, its existence is sufficient to consider it made.
I would suggest adding
.PHONY: all clean
to the end of Makefile
.
You are allowed to call the file anything you like, as long as that is Makefile
😉 Actually, there’s a couple of non-standard names that may be used as fallbacks, or you can provide a name with the -f
flag to make
, but I wouldn’t recommend either of those if you’re in a position to avoid them.
Other comments (for which you didn’t ask, but you’re getting anyway):
- Avoid invoking
make
literally in a command; always use$(MAKE)
. This helps when you use-n
, for instance. - Don’t prevent your makefile’s users from building for a kernel other than that which is running now. Create a variable for it (e.g.
KVER := $(shell uname -r)
orKSRC := /lib/modules/$(shell uname -r)/build
so it can be overridden on the command line.