How to emulate ARM unaligned memory access exceptions?

I’m writing a cross-platform application which works on x86 machines, but crashes with “Bus error” on the actual ARM hardware (Raspberypi 2) …

[ 4105.019037] Alignment trap: not handling instruction edd37a00 at [<00014218>]
[ 4105.019059] Unhandled fault: alignment exception (0x001) at 0x0002814e
[ 4105.028227] pgd = b736c000
[ 4105.033347] [0002814e] *pgd=3708d835, *pte=335d075f, *ppte=335d0c7f

… but runs without any problems in Qemu.

I run this command to enable SIGBUS signal and notification in the kernel running under Qemu, but it doesn’t seem to have any effect:

echo 5 > /proc/cpu/alignment [2]

How do I emulate these errors in Qemu (or in another free emulator)? I would like to be able to run my automated tests inside a continuous integration environment running on a x86 machine where I’m unable to use the actual hardware. Alternatively I could rent an ARM server but I would like to avoid this.

Later edit for further clarification: the instruction which causes this problem on the real hardware is also executed in the emulator where it seems to work without triggering any exceptions.

Answer

QEMU does not currently emulate unaligned access traps for ARM guest code. This is a reflection of the fact that its traditional primary purpose is “run correct guest code as quickly as possible”; putting in alignment traps slows down correct guest code and only makes a difference on buggy guest code running on older Arm cores (since ARMv7 and above handle unaligned accesses correctly in hardware).

That said, we do nowadays have better support in the generic code for emitting relatively efficient alignment checks; we just haven’t bothered to wire these up to the Arm codegen yet. If somebody wanted to write QEMU patches to add that support we’d accept them. (Roughly, the code in target/arm/translate.c would need to add MO_ALIGN to the memop flags when generating guest loads and stores when the guest CPU is in a state that means unaligned accesses should trap; this may differ between different architecture versions and for different types of load and store insn.)