Makefile : No rule to make target

I have a problem with Makefile. It should compile a .c file to an object file only if the .c file has been modified. But I have an error when I use all rule:

make: *** No rule to make target `obj/main.o', needed by `ft_ls'.  Stop.

When I use manually it works:

clang -Wall -Wextra -Werror -Iinclude -o obj/main.o -c src/main.c

My work directory:

Makefile include/*.h  libft/libft.a    src/*.c

Makefile content:

NAME = ft_ls
SRC_PATH = src
OBJ_PATH = obj
CPPFLAGS = -Iinclude
LDFLAGS = -Llibft
LDLIBS = -lft
CFLAGS = -Werror -Wall -Wextra
CC = clang
SRC_NAME = main.c
     ft_type.c
     ft_right.c
     ft_putright.c
     ft_date_converter.c
OBJ_NAME = $(SRC_NAME:.c=.o)
SRC = $(addprefix $(SRC_PATH)/,$(SRC_NAME))
OBJ = $(addprefix $(OBJ_PATH)/,$(OBJ_NAME))

all: $(NAME)

$(NAME): $(OBJ)
   $(CC) $(LDFLAGS) $(LDLIBS) $^ -o $@
   make -C libft

$(OBJ_PATH)%.o: $(SRC_PATH)%.c
   @mkdir $(OBJ_PATH) 2> /dev/null || true
   $(CC) $(CFLAGS) $(CPPFLAGS) -o $@ -c $<

clean:
   rm -fv $(OBJ)
   make -C libft clean
   @rmdir $(OBJ_PATH) 2> /dev/null || true

fclean: clean
   rm -fv $(NAME)
   make -C libft fclean

re: fclean all

.PHONY: all, clean, fclean, re

Answer

this dependency line:

$(OBJ_PATH)%.o: $(SRC_PATH)%.c

concatenates $(OBJ_PATH) with the object name, but there’s a / missing, should be

$(OBJ_PATH)/%.o: $(SRC_PATH)/%.c

else it expands (ex: for main) to:

objmain.o : srcmain.c