I have a few makefiles that store shared variables, such as CC=gcc , how should I name them?
The candidates are:
common.mk Make.common Makefile.common
.. which is more classic? Is there a standard?
Similarly, I have some shell scripts, which should i choose among the following:
do_this_please.sh do-this-please.sh DoThisPlease.sh doThisPlease.sh
Is there a generally accepted ‘case’ and suffix for these?
Advertisement
Answer
What you’ve got are the bits that glue a build together. Build scripts, auto-generated configs, makefiles that other makefiles include – questioning how that stuff should be named is a good idea.
Most of all, be consistent.
I’ve seen a lot of .mk extensions for files included via the Makefile. However, as Gyom suggests, it’s a very subjective question.
Whatever makes the syntax highlighter in your editor of choice happy is probably a good choice. If you’re on a team where everyone uses something different, ask folks. For me, naming a makefile include with a .mk extension highlights correctly for everyone. Naming shell scripts with a .sh suffix helps in a similar way.
In short, make the file names obvious and try to make syntax highlighting work on as many editors / IDEs as possible. Makefile.common might not do that, common.mk may have a better shot.