I’m writing a custom high-speed Linux SPI driver for an embedded SoC. To send data to the SPI peripheral (DMA_MEM_TO_DEV) I’m the Linux DMA Engine API. https://www.kernel.org/doc/Documentation/dmaengine/client.txt Based on the documentation, the steps for setting up and executing a DMA transaction…
Tag: dma
How to read stale values on x86
My goal is to read in stale and outdated values of memory without cache-coherence. I have attempted to use prefetchnta to perform a non-temporal load, but it failed to fetch outdated values. I am looking into performing some kind of Streaming Memory-to-Memory Direct-Memory-Access, but am having a little troub…
DMA Engine Timeout and DMA Memory Mapping
I am trying to use a Linux DMA driver. Currently, when I send the transaction out and begin waiting, my request times out. I believe this has to do with the way I am setting up my buffers when I am performing DMA Mapping. In Xilinx’s DMA driver, they take special care to look at memory alignment. In par…
Why driver need to map DMA buffers when dma-engine is in device?
DMA buffers are memory mapped by the driver. For example, in pci-skeleton.c, which uses rtl8319 we have: But DMA engine can reside in soc or in device. **Is it that dma buffers should be allocated even if DMA engine is in device ? Why ? ** rtl8139cp datasheet (I think the dma is part of the device, but not su…
Linux DMA: Using the DMAengine for scatter-gather transactions
I try to use the DMAengine API from a custom kernel driver to perform a scatter-gather operation. I have a contiguous memory region as source and I want to copy its data in several distributed buffers through a scatterlist structure. The DMA controller is the PL330 one that supports the DMAengine API (see PL3…
How to disable cache memory in kernel modules
I’am currently trying to develop a Linux driver to use a custom module developed in FPGA. For that, I use a Xilinx Zynq SoC with a Linux distribution that runs on the 2 ARM cores and my VHDL modules are implemented on the FPGA part, but this is not really important to understand my problem. My FPGA modu…