I’m having this weird problem with this makefile. Despite having all the required .c files, the compiling process stops at the first instruction, with this error. make: *** No rule to make target ‘printerTest.umps’, needed by ‘all’. Stop. This exact code with the same exact files works in Debian Linux, though in Manjaro Arch Linux it return the error shown
Tag: gnu-make
variable to switch the pre-requisites for a target in a Makefile
I wish to use ‘MY_TYPE’ to switch the prerequisites for the target ‘top’. based on MY_TYPE Can I select the pre-requisites required For example, for MY_TYPE=FOO , I wish to have $(BUILD) $(TARGETS) $(X_LOCALS) as pre-requisites for top MY_TYPE=BAR , I wish to have $(BUILD) $(TARGETS) $(Y_LOCALS) as pre-requisites for top How can I achieve it? Below is a simple
Automatic variable not expanding properly in Makefile
I am using the following code: However, when I run the code, I receive the following error, implying that $< is not evaluating to anything: When I use the following code… …the Makefile evaluates to the following command… …which is precisely what I would like. However, I do not want to use addsuffix twice. I would like to use $<
Piping two command from makefile is not working
I use the following commands in my makefile in the commands im getting array of values and remove the array [] from it, I want to run this command in my terminal and I use the following fzr provide apps | (subst ],,$(subst [,,$(apps))) | $(apps) and I got error what am I missing here ? if I run only
Understand the basic concept of a Makefile
I have the following makefile which I am trying to upgrade, but there is a certain element which I am not able to understand what means: I understand that $(OBJDIR)/%.o: is obtained by executing the f90 compiler with flags etc. But why do I need the %.o rule, and what does @make mean. Am I missing a general understanding of
makefile substitute target pattern twice in its dependency
I have the following project architecture My aim is to generate a png image for each directory present into doc/uml into build/doc/uml The parent makefile is the following one And the submakefile is the following one However it’s failing when I’m launching it with make doc It seems that the problem comes from the fact that ‘%’ can’t be replaced
Makefile, add headers located in parent directory (Not allowed to move inside!)
prog.c myheader1.h myheader2.h Looking for solution on how to add a header from parent directory I found this question. But it didn’t work for me and I am still getting error of not finding the header file. No rule to make target ‘myheader1.h’, needed by ‘prog.o’. Stop. makefile What am I doing incorrect? and how to add the second header
Install older version of gnu-make in Ubuntu 18.04
I want to install make 3.81 on Ubuntu 18.04. So I download this version of make and run ./configure and then make. But when compiling it gives me this error: Same situation at building version 3.82. My current version of make is 4.1. Is anybody know what could be wrong? Thanks EDIT: glob/libglob.a(glob.o): In function `glob_in_dir’: /opt/make-3.81/glob/glob.c:1361: undefined reference to
How can i initialize and then iterate an array in linux makefile?
I need to create an array with directories and then inereate it, creating one more array in each step which will include all files found via ‘find’ command for each derictory and also iterate this array. I was trying to do something like this: but it does not work. Even this gets error: gets error: Answer This is because make
conditional check within makefile
I am updating makefile of the project where I need to perform different steps based on the customer or manufacturing build, I have written simple makefile as follows and with that I am seeing unexpected output, could someone help figure out issue with makefile. I am getting following output of the makefile This is unexpected output, as build type is