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How does this Makefile work?

This is the makefile:

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It produces log result:

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I can only understand first two lines in the log. How all this files:

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files get to compiling? They are contained in GOOGLEAPIS_CCS variable and it is only used in makefile in

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string. Can you explain step by step how this actually work?

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Answer

The following rule makes a static library that depends on the object files that will result from compiling all of the discovered source files:

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The way this works is that $(GOOGLEAPIS_CCS:.cc=.o) means “take the variable GOOGLEAPIS_CCS, and within it, replace every occurance of .cc with .o“. That is, convert the discovered lists of sources into a list of the object files that will be generated from them. Because this is on the prerequisite line, make will try to find a rule for how to produce these objects.

There are no explicit rules in the Makefile for building the .o files, so make will use one of the built-in implicitly defined pattern rules. Specifically:

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So that causes all of the compilation you see in your output. Once these are built, the rule we were looking at above archives them into a static library. That static library is one of the prerequisites for the main build target, which is what triggers all of the above to be evaluated.

It may be obvious, but for completeness, all of the initial variable declartions use $(shell find ...). This literally runs the find command via the shell to recursively traverse the specified directory, and list the files that match the given pattern (e.g., *.cc). The result is that these variables are defined as the list of matching filenames.

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