I am trying to figure out the event to use with the perf stat command to count L3 cache accesses on an AMD Zen 2 processor. As per the PPR (http://developer.amd.com/wordpress/media/2017/11/54945_PPR_Family_17h_Models_00h-0Fh.pdf), section 2.1.13.4.1, page 168, the event is x01 and the umask is x80 for “[L3 Cache Accesses] (L3RequestG1)”. From what I understand, the event to use in perf stat
Tag: amd-processor
What is C-state Cx in cpupower monitor
I am profiling an application for execution time on an x86-64 processor running linux. Before starting to benchmark the application, I want to make sure that the Dynamic Frequency scaling and idle states are disabled. Check on Frequency scaling This tells me that the Frequency scaling(Intel’s Turbo Boost or AMD’s Turbo Core) is disabled. In fact, we set it to
Why is an AMD Ryzen 2700x 2x slower than a 3-year-old laptop Intel i7-6820HQ with Python?
I just finished installing a desktop computer based on an AMD Ryzen 2700x and 32GB RAM (running Ubuntu 18.04). At work, I have a 3-year-old laptop workstation with an Intel i7-6820HQ and 16GB RAM (running Windows 10). I installed Anaconda on both platforms and ran a custom Python code which relies heavily on basic numpy matrix operations. The code does