I am building a C++ project from Github and want to deploy the code to a remote Linux machine. This is all new to me. The project has a main.cpp, which includes the various headers/sources like a library. The CMake outputs an executable (to represent main.cpp) AND a separate static library. The project also uses OpenSSL, which I have linked
Tag: makefile
If not exists, create a folder – Error in makefile
I searched over the internet for a command to create a folder if it doesn’t exist. I found it and put in my makefile When the folder doesn’t exist it’s created correctly. But I get an error if the folder already exists. I don’t get why the command would give an error if the condition [ ! -d “myfolder” ]
Any possibilities that makefile can use different compilers by flag and find variable gcc paths?
Are there any possibilities that makefile can use different compilers by flag and find variable gcc paths? System is Linux. So the goal should be anything like to say in command line “make CC=…” and it should use one of two possible compilers and should find the path to the second one (first compiler is standard gcc) in a way
Unable to compile kernel module: no .ko file output
I’ve built an android kernel (source code), now I’m trying to cross-compile a kernel module for it, v4l2loopback to be precise. I’ve used this toolchain to build the kernel (kernel version is 4.9). Here on github you can see that someone actually succeeded in compiling the module, and I’ve been trying to replicate their success myself. But in the last
How do I compile and deliver my application without requiring installation of shared libraries on other machines
On my Ubuntu machine I installed libGLEW. However, I did not install it on my other Ubuntu machine. It works on my compiling machine, but now I received the following error after copying my executable to my other machine. I want to find a solution where I don’t have to require my other machine to install the library. Maybe I
C++ including Python.h compiling using makefile
I am trying to compile a C++ program which uses Python.h to execute some python scripts. Before adding the python, I had a makefile which works perfectly. I added the code to run the python script, which involves including the Python.h file. I edited the makefile to include this file, without success. My makefile: I already installed following libraries: sudo
Cannot compile Makefile using make command on Windows
Problem summary I am trying to install an open-source parallel finite-element code called TACS and available at this github repository. To comply with the indicated prerequisites, I followed the instructions at this github repository, which allowed me to install SuiteSparse and METIS on Windows with precompiled BLAS/LAPACK DLLs. For the MPI, I installed both the Intel MPI Library and Open
Makefile: “No rule to make … needed by ‘all'” despite all files being there
I’m having this weird problem with this makefile. Despite having all the required .c files, the compiling process stops at the first instruction, with this error. make: *** No rule to make target ‘printerTest.umps’, needed by ‘all’. Stop. This exact code with the same exact files works in Debian Linux, though in Manjaro Arch Linux it return the error shown
Traversing a directory using Makefile
I am making use of a makefile to traverse a directory , store the file names in a variable , extract the file number using regex and print the file number . Below is the code block I am using : LINE 7 is the command in makefile I want to include in the for loop. I want the actual
make: how to append text to beginning and end of list?
In the makefile I’m writing, I am using the shell command find to build a list of source files to compile. In particular, I’m using the line: Now this works just fine. However, I would like to add support for excluding files that have a pattern that appears in a list called EXCLUDE. I’d like to use the prune option