I’m trying to write a single command in my makefile to get the current folder and remove all “.” from the name. I can get the current folder with $${PWD##*/} and I can remove the “.”s with $${PWD//.} but I can’t figure out how to combine these two into one. The reason I nee…
Tag: makefile
How can i initialize and then iterate an array in linux makefile?
I need to create an array with directories and then inereate it, creating one more array in each step which will include all files found via ‘find’ command for each derictory and also iterate this array. I was trying to do something like this: but it does not work. Even this gets error: gets error…
./configure + endless loop
Am trying to build/install LFTP in Centos 7 and can’t get past an endless loop at ./configure stage. Steps I’ve taken: Then I see an endless loop of: Any suggestions/tips appreciated. I’ve tried to use a prefix with ./configure too but that doesn’t help. Answer As discussed in the comm…
Automate make execution with variable parameter
Here “SEED” means a random number: I will run the target test1 in terminal likewise. But the problem is here I want to run that target 10 times by using any conditional loops. If i want to run the test1 2nd time again I need to give like this: 3rd time: 4th time: Likewise, each and every time I ne…
Predefine a macro in kernel module
I would like to define a macro for my kernel module by using the -D flag, but I can’t figure out how to do it in a custom loadable kernel module. Just to be clear, to set the macro TEST to 1 I usually do something like: cc -D TEST=1 file.c -o file And inside the file.c I have Now,
How does this Makefile work?
This is the makefile: It produces log result: I can only understand first two lines in the log. How all this files: files get to compiling? They are contained in GOOGLEAPIS_CCS variable and it is only used in makefile in string. Can you explain step by step how this actually work? Answer The following rule ma…
Makefile : No rule to make target
I have a problem with Makefile. It should compile a .c file to an object file only if the .c file has been modified. But I have an error when I use all rule: When I use manually it works: My work directory: Makefile content: Answer this dependency line: concatenates $(OBJ_PATH) with the object name, but there…
Makefile: Cpp Files in Different Directories, Redirect Object Files to ./obj and Executable to ./bin
my directory structure looks like this I would like to write a Makefile that will 1) create three object files, main.o, class1.o and test-wrapper-class.o and place those files in the obj directory 2) use those object files to create an executable that will be placed in the bin folder 3) have a clean that will…
Makefiles with source / object files in different directories
I have a project with the following directory structure: A file in the $doc/tests directory e.g test1.rst is created from $tests/test1/test1.e. I’m having problems with the makefile specifying that the source files are in $tests/*/*.e and the destination files are in $doc/tests/*.rst. I’ve seen se…
Makefile – wildcard and recipe build
I have the following makefile I got this message : make: Circular src/paquet/packet_implem.o <- src/paquet/packet_implem.o dependency dropped. gcc -std=c99 -Wall -Werror -Wshadow -Wextra -O2 -D_FORTIFY_SOURCE=2 -fstack-protector-all -lz -rdynamic -I/home/jy95/local/include -L/home/jy95/local/lib; /usr/lib…